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[Other] shizhong

Description: 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
Platform: | Size: 67584 | Author: wuyub | Hits:

[source in ebook] shizhong

Description: 简单的VB时钟控件操作，对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
Platform: | Size: 120832 | Author: 黄卫 | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: 这个VHDL与其他上传的代码不同，这个代码更适合于初学者。电子时钟已经在硬件上得到成功仿真。-From the VHDL code with other different, the code is more suitable for beginners. Electronic clock has been successful in the hardware simulation.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: 数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
Platform: | Size: 310272 | Author: zhaozheng | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: 时钟程序设计，为用vhdl语言设计编写的电子时钟显示分秒位-Clock programming, vhdl language designed for use in the preparation of accurate digital electronic clock display
Platform: | Size: 1024 | Author: llyluya | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: 一个用VHDL语言编写的时钟程序，软件平台是Quartus II 7.2 ，它是由前面上传的小模块组合起来制作的，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -A clock with the VHDL language program, the software platform is Quartus II 7.2, it is uploaded from the front of the small module combined production, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to get to know and understanding of the VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
Platform: | Size: 408576 | Author: QQ | Hits:

[Other] shizhong

Description: 用eda 技术实现电子时钟的基本功能,包括定时，跑秒等功能。（这里只有源代码）-This is a simple chengxu write by vhdl
Platform: | Size: 1024 | Author: 冯文 | Hits:

[VHDL-FPGA-Verilog] shuziluji

Description: 纯VHDL文件 拥有闹铃 整点报时 日历 使用方法（打开文件shizhong.gdf文件编译即可（本人使用maxplus-Pure VHDL files have calendar alarm whole hour to use (you can open the file shizhong.gdf file compilation (I use maxplus))
Platform: | Size: 590848 | Author: 虫子 | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: vhdl描述的数字钟，功能一样，方法不同-vhdl description of the digital clock, the same function, different methods
Platform: | Size: 2048 | Author: 苏杰 | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: vhdl电子时钟（24小时制，时、分、秒）描述-VHDL electronic clock (24 hours to make, points seconds) description
Platform: | Size: 1024 | Author: 李晓宇 | Hits:

[Static control] dian-zhi-shizhong-vhdl-yu-yan-shiji

Description: 电子时钟VHDL程序与仿真包含了电子时钟设计的全部代码-good good good good good good good good good good good good good good good
Platform: | Size: 59392 | Author: 张光强 | Hits:

[Books] shizhong

Description: 用VHDL语言实现12/24小时制数时钟，可显示时、分、秒；能够进行整点报时，具有12/24小时切换功能-Number of 12/24 hour clock clock using VHDL, can display hours, minutes, seconds able to carry out the whole point of time, with 12/24 hour switch
Platform: | Size: 2287616 | Author: 王婷 | Hits:

[Other] shizhong

Description: VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。-verilog HDL
Platform: | Size: 2048 | Author: lu | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: VHDL时钟芯片设计，走时加显示,用于XC3S50-TQ144，引脚已定义，可直接载入运行-VHDL clock design with display
Platform: | Size: 1345536 | Author: 瞿昕宇 | Hits:

[Other] shizhong

Description: VHDL硬件语言实现时钟功能（只有分秒），在Quarter 2上的编程。-VHDL hardware language clock function (only minutes and seconds), the programming of the Quarter 2.
Platform: | Size: 1024 | Author: caidanchun | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: 这是用VHDL编写的数字逻辑时钟电路，实现计时和由23:59到00:00转换的功能，已经在FPGA中测试通过！-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
Platform: | Size: 370688 | Author: 李佳倩 | Hits:

[VHDL-FPGA-Verilog] shizhong

Description: VHDL设计带报警的59分钟定时器，系统以秒速度递增至59分钟后,启动报警1秒钟,置位后又以秒速度递减至零并报警1秒钟。-VHDL design with alarm 59 minutes timer
Platform: | Size: 14336 | Author: 王一 | Hits:

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